1. Technical Field
The invention relates generally to the design of integrated circuits; and, more particularly, it relates to the design of integrated circuits having both fixed logic and programmable logic components.
2. Related Art
Programmable devices are a class of general-purpose integrated circuits that can be configured for a wide variety of applications. Such programmable devices have two basic versions, mask programmable devices, which are programmed only by a manufacture, and field programmable devices, which are programmable by the end user. In addition, programmable devices can be further categorized as programmable memory devices or programmable logic devices. Programmable memory devices include programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electronically erasable programmable read only memory (EEPROM). Programmable logic devices include programmable logic array (PLA) devices, programmable array logic (PAL) devices, erasable programmable logic devices (EPLD) devices, and programmable gate arrays (PGA).
As is known, field programmable gate arrays (FPGAs) allow an end user to create a customize logic design via programming and to freely change the design by reprogramming the design while avoiding the initial cost, time delay and inherent risk of application specific integrated circuits (ASICs). While FPGAs have these advantages, there are some disadvantages. For instance, an FPGA programmed to perform a similar function as implemented in an ASIC requires approximately 25 to 50 times more die area than the ASIC. As such, the manufacturing expense of an FPGA is greater than that of an ASIC. In addition, an FPGA requires significantly more printed circuit board space and consumes more power than an equally functional ASIC.
To mitigate some of the disadvantages of FPGAs with respect to ASICs, some FPGA manufacturers are including ASIC like functions on the same substrate as the programmable logic fabric. For example, FPGAs are now commercially available that include random access memory (RAM) blocks and/or multipliers in the programmable logic fabric. As such, the programmable logic fabric does not have to be programmed to perform RAM functions and/or multiplier functions, when such functions are needed. Thus, for these functions, significantly less die area is needed within the FPGA.
While included such fixed logic functions in the programmable logic fabric offers end users greater programming options with less die area consumption, end users are demanding greater FPGA performance and flexibility from FPGAs. In particular, end users would like to see more fixed logic functionality, (i.e., ASIC like functionality) embedded within the programmable logic fabric of FPGAs, while retaining the versatility of traditional FPGAs.
Given the relative newness of providing fixed logic functionality within a programmable logic fabric of an FPGA, there is very little known in the art, if anything at all, concerning the appropriate combination of these two, oftentimes, diametrically opposed technologies. That is to say, the fixed logic functionality is geared towards and based in one particular direction of development, and the technology of programmable logic fabric is directed in another direction entirely. The integration of these two circuit types has left many in the art with very little direction on how to perform and to provide this combination of elements as desired by end users.
Thus, there is a need in the art for a methodology of overcoming these and other difficulties in the design of integrated circuits having both fixed logic and programmable logic components.